1. Field of the Invention
This invention relates generally to data communications and more particularly to transmission of high frequency signal over transmission lines for high-speed data communication.
2. Description of the Related Art
Modem computer systems often utilize one or more buses to connect to peripheral devices to enhance its resources. For example, the resources of a computer system may be substantially increased by connecting the computer system to one or more peripheral devices such as disk drives, tape drives, printers, scanners, optical drives, and the like. These peripheral devices are attached to the computer system by means of a peripheral bus (e.g., cable).
One of the most widely used peripheral buses is the well known small computer systems interface (SCSI) bus, which is defined in conformity with well known SCSI protocols (e.g., SCSI-1, SCSI-2, SCSI-3, etc.). These SCSI protocols are universal parallel interface standards for connecting disks and other high performance peripherals to computers and are incorporated herein by reference. The SCSI protocols are designed to provide an efficient peer-to-peer I/O interface between a host computer and peripheral devices in a computer system.
FIG. 1 shows a block diagram of a conventional computer system 10 including a host computer 12, one or more SCSI devices 14, 16, and 18, and a SCSI bus 20. The host computer 12 includes an SCSI host adapter 22 for communicating with the SCSI peripheral devices 14, 16, and 18. The host adapter 22 in the computer system 10 controls communication between the host computer 12 and the SCSI devices 14, 16, and 18. For example, the host adapter 22 provides a physical connection between the host computer 12 and the SCSI bus 20. In addition, it is configured to receive data, address, and control signals from the host computer 12 and convert the signals into corresponding SCSI compatible data, address, and control signals. Conversely, the SCSI host adapter 22 is also configured to receive SCSI compatible data, address, and control signals from the SCSI devices 14, 16, and 18 through the SCSI bus 20 and convert them into corresponding host-bus compatible data, addressing, and control signals. The SCSI host adapter 16 is well known in the art and may be implemented, for example, by using AIC-7890A(trademark) packaged semiconductor device, which is available from Adaptec Inc., of Milpitas, Calif. Although the computer system 10 is illustrated using a SCSI bus, it should be appreciated that computer system 10 may employ other interface standards having characteristics similar to SCSI such as Intelligent Peripheral Interface (IPI) standard.
In the computer system 10, the host adapter 22 and SCSI devices 14, 16, and 18 typically use bus drivers and bus receivers to allow devices to communicate data and control signals. FIG. 2 shows a more detailed schematic diagram of the host computer 12 and peripheral device 18 connected via the SCSI bus 20 for driving and receiving a signal. The SCSI bus 20 is a 16-bit SCSI bus with a plurality of control and data lines 52, 54, 56, 58, 60, and 62 to transmit control and data signals. For example, data lines 52 to 54 are used to transmit data signals from data[0] through data[15] while parity line 56 is used to carry a parity signal. On the other hand, control lines 58 to 62 are used to transmit control signals. For example, the control line 58 is used to carry ACK (acknowledge) signal while the control line 60 transmits REQ (request) signal. Other well known SCSI control signals are also carried on control lines 62.
Both the host computer 12 and peripheral device 18 typically include a driver and a receiver for each data and control line in the bus 20. In the example, the host computer 12 is shown with a driver 72 and the peripheral device 78 is shown with a receiver 78 to illustrate transmission of a data signal over data line 54 from the driver 70 to the receiver 78. It should be noted, however, that the signal transmission may proceed in either direction because the host adapter 22 and peripheral devices 14, 16, and 18 each typically includes a driver and receiver pair for bi-directional communication.
The output of the driver 72 is electrically coupled to the data line 54 while the input of the receiver 78 is electrically coupled to the data line 54 in the bus 20. To illustrate transmission of a signal value 70 over bus line 54, the driver 72 receives the signal value 70 from the host computer 12 (i.e., host adapter 22) and drives the signal value 70 onto the data line 54 corresponding to data[15]. The receiver 78 then receives and outputs the signal value 70 from the data line 54 for use as data[15] by the peripheral device 18.
FIG. 3 shows a more detailed schematic circuit diagram of the driver 72 and receiver 78 for transmitting signal value 70 over line 54. Typically, SCSI bus 20 employs a voltage differential technique to transmit signals. Accordingly, the driver 72 transmits the signal value 70 using a signal line 82 and a complement signal line 84 to the receiver 78. In this configuration, the signal lines 82 and 84 are used to transmit information for bus line 54. Other bus lines typically employ a pair of signal lines to transmit information.
To determine which devices are asserting which bits on the bus during arbitration phase of SCSI protocol, the SCSI bus also implements a bias voltage in the termination at each end of the SCSI bus. Without a termination bias voltage, it would be difficult to determine which device is asserting a data bit because bits not being asserted would be floating. To provide the termination bias voltage, computer 12 includes a voltage source V(A) 86 (e.g., 1.5 volts) and a voltage source V(B) 88 (e.g., 1.0 volt) which are connected in series using a resistor 90 (e.g., 270 ohms), resistor 92 (e.g., 138 ohms), and resistor 94 (e.g., 270 ohms). This termination bias voltage circuit is connected to signal lines 82 and 84 as shown. Thus, a junction 91 is typically at 1.3 volts due to the termination bias voltage, and a junction 93 is typically at 1.2 volts due to the termination bias voltage. The termination bias voltage also results in an approximate termination resistance of 110 ohms.
Similarly, the peripheral device 18 also includes a termination bias voltage. As in the host computer 12, resistors 95, 96, and 97 connect in series between voltage sources V(A) and V(B). These voltages and resistances may have similar values as for the host computer 12 and are connected to signal lines 82 and 84 as shown. Also shown in FIG. 3 are multiple bus taps 98 symbolizing the variety of other devices, computers, and peripherals that may also tap onto SCSI bus 20.
In the driver and receiver configuration, the driver 72 uses a low-voltage swing differential (LVD) driver and the receiver 78 is a low offset voltage, high-speed, differential input receiver. The driver for this type of SCSI bus uses an asymmetrical output, where one direction has more drive strength than the other. The reason for this asymmetrical output is because of the termination bias voltage discussed above.
The termination bias voltage and the asymmetrical driver output that it necessitates often cause undesirable effects. The reason for the need for a termination bias voltage has to do with the dual use of the data lines of a SCSI bus. A SCSI bus includes data lines that are used during a data phase of communication, i.e., high-speed transmission of data. A SCSI bus also includes various control lines that are used to transmit control signals at a lower speed during a protocol phase of communication on the bus. However, the data lines of a SCSI bus have a dual use. During the protocol phase of communication, the data lines are also used to transmit control signals used for arbitration on the bus. Thus, the data lines of a SCSI bus must be able to operate in a high-speed data phase and also in a low-speed protocol phase. Operation of these lines in the protocol phase requires a termination bias voltage.
The data lines have this dual use because of the way peripherals indicate when they wish to use the SCSI bus. When a peripheral on a SCSI bus wishes to use the bus, it asserts one of the data lines. Each peripheral on the bus is associated with one of the data lines, thus it can be determined which peripheral wants to use the bus by which data line is being asserted. However, when one peripheral is asserting one data line, the other data signals must be driven to a known state so that the SCSI bus and its attached devices can determine which data line is being asserted. In other words, if the data lines are simply floated it would be difficult to determine which of many data lines is being asserted.
Therefore, pull-up voltages are used at each end of the SCSI bus so that any non-driven data lines are put into a negated state. Thus, when one peripheral device asserts one data line, all of the other data lines will be in a negated state and it may then be determined which peripheral wishes to use the bus. These pull-up voltages are called termination bias voltages and are due to the dual use of the data lines of a SCSI bus. A termination bias voltage is present at each end of a SCSI bus and is used with single-ended drivers and also with differential drivers.
Conventional SCSI buses typically employ high-voltage differential drivers. A high-voltage driver may have a voltage differential of about 2.5 volts minimum, whereas a low-voltage differential driver may have a differential from about 260 mV to 780 mV. Differential drivers and receivers are described in more detail in U.S. Pat. No. 5,949,253 to Walter F. Bridgewater, Jr. and entitled xe2x80x9cLow Voltage Differential Driver with Multiple Drive Strengths,xe2x80x9d which is incorporated herein by reference.
As described in U.S. Pat. No. 5,949,253, the use of high speed communication buses such as SCSI bus often generates undesirable xe2x80x9cfirst pulse problem.xe2x80x9d The first pulse problem is generally caused by too much attenuation of a signal for its first pulse after a stead state. If a driver maintains a value for several clock cycles, for example, the first pulse after the constant signal value when the output driver changes its state will not be of good quality. That is, when the signal finally changes after being in one state for a number of clock cycles, the next pulse will typically be of poor quality. This may lead to inaccurate transmission of transmission signals.
The first pulse problem is typically caused by the frequency roll-off or high frequency attenuation characteristics of transmission cables. This attenuation is combined with a last signal level being driven all the way to its maximum limits while the cable is being driven in a constant state. If a cable is driven to a constant state for a long time, it goes to its maximum possible voltage level. Then, when a high frequency signal is driven in the other direction, it generally cannot drive the maximum voltage level in the other direction. Thus, the amount of over drive in the other direction is small.
FIG. 4 shows a series of pulses 100 for a signal coming from a driver of a low-voltage differential (LVD) SCSI bus. The SCSI bus uses a low-voltage swing differential for communication, which results in a particular value to be transmitted being represented by the complementary pulses shown. Signal 101 and {overscore (signal)} 102 may originate from a driver such as driver 72 of FIG. 3. By convention, signal 101 represents possible pulses occurring on signal line 82 while {overscore (signal)} 102 represents the complement of these pulses as might be occurring on signal line 84.
In a steady state, signal and {overscore (signal)} have a difference of about 500 mV 103. This voltage difference for a pair of signals, representing a value to be transmitted over a differential bus, allows the receiver to accurately determine the value to be transmitted. If signal and {overscore (signal)} do not have a sufficient voltage differential due to the first pulse problem, then the receiver may not be able to determine what value is being transmitted from the driver. For example, in FIG. 4, signal and {overscore (signal)} have remained in a constant state until a first pulse 104 occurs. At first pulse 104, signal 101 is only able to obtain a voltage level 105 which is far lower than the voltage level that {overscore (signal)} 102 had maintained during its steady state. Likewise, {overscore (signal)} 102 is only able to reach a voltage level 106 which is far short of the voltage level maintained by signal 101 in its static state. In this example, peaks 105 and 106 at first pulse 104 are only separated by about 100 mV 107. This minimal voltage separation of 100 mV is to be contrasted with the much larger voltage differential of 500 mV before the first pulse occurred. Typically, a differential voltage of only 100 mV is not sufficient to allow a receiver to correctly determine a signal. However, after the first pulse, subsequent pulses 108, 110, 112, etc., are generally able to achieve a much greater voltage differential.
To address the first pulse problem, conventional drivers have typically applied precomp cutback in a single step with normal slew rate. Unfortunately, however, such precompensation technique typically introduces noise in the signal, thereby reducing noise margin. In addition, the single-step cutback approach generally produces jitters at the receiver end because the amount of precompensation does not match the attenuation of the transmission cable or bus.
In view of the foregoing, it would be desirable to have a differential driver for a bus that can precompensate transmission signals while reducing the noise and jitter.
The present invention fills these needs by providing a differential driver for a bus that precompensates transmission signals while reducing the noise and jitter. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a differential driver for transmitting signals. The differential driver includes a main buffer, a set of secondary buffers, and control logic circuitry. The main buffer is arranged to drive a first input differential signal for output as a differential output signal over a differential output line. The set of secondary buffers is arranged to receive second input differential signals, tristate signals, and mode signals with each secondary buffer receiving one second input differential signal, one tristate signal, and one mode signal. The secondary buffers are further configured to operate in a normal slew rate or a slow slew rate. Each tristate signal is configured to drive the associated secondary buffer to high impedance to turn off the associated secondary buffer when the tristate signal is asserted. Additionally, each secondary buffer is configured to operate in a slow slew rate in response to the associated mode signal. The control logic circuitry is arranged to receive input signals and a clock signal for generating the first input differential signal, second input differential signals, tristate signals, and the mode signals such that the secondary buffers cutback the differential output signal on the differential output line when the input signals are in a steady state for more than a specified number of clock cycles. In this configuration, the secondary buffers are arranged to cutback the differential output signal by tristating in response to the tristate signals and by operating in the slow slew rate in response to the mode signals.
In another embodiment, the present invention provides a differential driver for transmitting signals. The differential driver includes first driving means, second driving means, and control means. The first driving means is arranged to drive a first input differential signal for output as a differential output signal over a differential output line. The second driving means is arranged to cut back the differential output signal when the input signals are in a steady state for more than a specified clock cycles. The second driving means is further arranged to receive second input differential signals, tristate signals, and mode signals and is operable in a normal slew rate or a slow slew rate. The control means is arranged to receive input signals and a clock signal for generating the first input differential signal, second input differential signals, tristate signals, and the mode signals such that the second driving means cuts back the differential output signal on the differential output line when the input signals are in a steady state for at least a specified number of clock cycles. In this configuration, the second driving means cuts back the differential output signal by tristating in response to the tristate signals and by operating in the slow slew rate in response to the mode signals.
The differential driver of the present invention thus cuts back output signal gradually and slowly in stages to reduce noise and jitter in the transmission system while improving noise margin. The process of cutting back the output signal is achieved by alternating between the tristate and slow slew rate mode for subsequent clock periods during which the output signal remains in a steady state until a change in state occurs. When the first pulse is output after the steady state of preferably at least first three clock periods, the differential driver is able to drive the first pulse with normal power level and normal slew rate to remedy the first pulse problem. In so doing, the noise and jitter in the transmission system is substantially eliminated. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.